How to use make command in Linux

In the Linux system, the make command is usually used with the Makefile. What are the usage methods of the make command? The following small series introduces you to the usage of the make command in Linux. Let's take a look at it.

in the development of a system, a system is typically divided into several modules, this improves the maintainability of the system, but due to the inevitable presence of correlation between the various modules, so that when a module change After that, other modules may be updated. Of course, for small systems, manual compilation of the connection is no problem, but if it is a large system, there are many modules, then the manual compilation method is not applicable. For this reason, in the Linux system, a make command is provided to automatically maintain the target file. Compared with manual compilation and connection, the advantage of the make command is that it only updates the modified file (in Linux, a file is created or After the update, there is a last modification time. The make command uses this last modification time to judge whether the file has been modified. However, the unmodified file is ignored, and the make command does not miss a file that needs to be updated.

There may be dependencies between files and files or between modules or modules. The make command is also maintained based on this dependency, so we need to understand what is a dependency; the make command certainly does not know for itself. These dependencies require the programmer to write these dependencies into a file called makefile. The Makefile contains some targets. Usually the target is the file name. For each target, a set of commands to achieve this goal and other targets or file names that depend on the target are provided. The following is a simple Makefile simple. Example:

#a simple Makefile

prog:prog1.o prog2.o

gcc prog1.o prog2.o -o prog

prog1 .o:prog1.c lib.h

gcc -c -I. -o prog1.o prog1.c

prog2.o:prog2.c

gcc - c prog2.c

The above Mamefile defines three targets: prog, prog1, and prog2. After the colon is a list of dependent files;

For the first target file prog, he has Two dependent files: prog1.o and prog2.o, any dependent file update, prog will also be updated, the command gcc prog1.o prog2.o -o prog is the command to generate prog. Make checks whether the target needs to be updated with a recursive method. Recursion updates the obsolete target from the bottom up, and the target is updated only when all targets that a target depends on are up to date. Taking the above Makefile as an example, we modified prog2.c. When executing make, since the target prog depends on prog1.o and prog2.o, we must first check if prog1.o and prog2.o are outdated, and the target prog1.o depends on prog1. .c and lib.h, since we didn't modify the two files, they didn't expire, then check the target prog2.o, he relies on prog2.c, since we modified prog2.c, so prog2.c More new than the target file prog2.o, that is, prog2.o expires, causing all targets that depend on prog2.o to be outdated; so make will update prog2.o first and then update prog.

If a line is too long and has reached the right edge of the text editor, a backslash () can be used as a newline character. All lines connected by the backslash will be treated as a line; in addition, in the Makefile Wildcards (? or *) are allowed for file names involved.

Sometimes in order to simplify the writing of commands, you can define some macros and use abbreviations in the Makefile. Here are a few commonly used abbreviations:

$@ represents the full name of the target

$* represents the target name for which the suffix has been removed

$" The first related target name representing the target

Now you can use the abbreviations to modify the above Makefile accordingly:

#Use the abbreviated Makefile

prog:prog1.o prog2.o

gcc prog1.o prog2.o -o $@

prog1. o:prog1.c lib.h

gcc -c -I. -o $@ $"

prog2.o:prog2.c

gcc -c $* .c

In a project, it is possible to use the same file ac in several targets. If the file is modified later, you need to modify all the acs in the Makefile. This is more troublesome and you can define macros to solve For this problem, macros can make Makefiles clearer:

#Makefiles using abbreviations and macros

MARCO = prog1.o prog2.o

prog:$(MARCO)

Gcc prog1.o prog2.o -o $@

prog1.o:prog1.c lib.h

gcc -c -I. -o $@ $"

prog2.o:prog2.c

gcc -c $*.c

For large projects, handwritten Makefiles are very cumbersome, and standard GNU software (like Apacle) Run a configure script file to generate the Makefile; GNU software automake and autoconf are tools for automatically generating configure. Developers only need to define the macro first. After automake processing, Makefine.in will be generated for autoconf, and then configure with autoconf. To use automake and autoconf you must install: GNU Automake, GNU Autoconf, GNU m4, perl and GNU Libtool.

The above is the usage of the make command in Linux. Explain through the example of Makefile. I believe that you have a certain understanding of the usage of the make command. The make command can also be used to execute the target file.