Among the many members of the MCU family, MCS-51 series MCUs occupy industrial measurement and control with its superior performance, mature technology, high reliability and high cost performance. The main market for automation engineering applications, and has become the mainstream model in the field of domestic microcontroller applications.
The parallel port of MCS-51 MCU has P0, P1, P2 and P3. Since P0 port is address/data bus port, P2 port is high 8-bit address line, P3 port has The second function, so that only the P1 port can be used as a bidirectional I/O port. This is not enough in most applications, so most MCS-51 microcontroller application system design will inevitably need to expand the P0 port.
Since the external RAM and I/O ports of the MCS-51 MCU are uniformly addressed, a part of the external 64K bytes of RAM space can be used as extended peripheral I/O. The address space of the port. In this way, the MCU can access the external P0 port interface chip as if accessing the external RAM memory unit to perform read/write operations on the P0 port. There are many dedicated chips for P0 port expansion. Such as 8255 programmable parallel P0 port expansion chip, 8155 programmable parallel P0 port expansion chip. This paper focuses on the specific method of parallel expansion of the P0 port using the 74HC244 chip with tri-state buffer and the 74HC377 chip with output latch.
1 Extension of Input Interface
The data bus of MCS-51 microcontroller is a common bus and cannot be used exclusively. This requires the chip to be connected above. With the "three-state" function, expanding the input interface is actually looking for a chip that can be used for control and has a three-state output. In order to enable the input device to be strobed, it can directly connect the data line of the input device to the data bus of the microcontroller; and when the input device is not strobed, it can isolate the data source and the data bus (ie, tristate buffering) The device is in a high impedance state).
1.1 The function of 74HC2244 chip
If the input data can be kept for a long time (such as keyboard), the typical chip commonly used for simple input interface expansion is 74HC244. A three-state data buffer can be constructed by the chip. The pin arrangement of the 74HC244 chip is shown in Figure 1.
There are two four-bit three-state buffers inside the 74HC244 chip, which can be used as their strobe signal with 1C and 2G respectively. When both 1C and 2G are low, the output Y and the input A have the same state; when both 1G and 2G are high, the output is in a high impedance state.
1.2 Application 74HC244 chip expansion input interface
Figure 2 is the principle circuit of 74HC2244 chip for input interface expansion, Figure 3 is the timing of reading P0 port. It can be seen from Figure 3 that when P2.7 and RD are both low, the 74HC2244 can send the data of the input terminal to the P0 port of the microcontroller. Among them, P2.7 determines the address of 74HC244, 0000H-7FFFH (32K total) address can access this unit, which is the side effect caused by the line selection method. Usually the highest address can be selected as the address of the chip to write the program, such as the address of this chip is 7FFFH. But this is only a habit, not a rule. Of course, 0000H can be used as the address of this chip. When the address is determined, the input operation procedure of its interface is as follows:
MOV DPTR,#7FFFH
MOVX A,@DPTR
The MOVX class instruction is an instruction for the MCS-5l microcontroller to operate on the external RAM. Since the external I/O is the same interface as the external RAM, this instruction is generally used to operate the external I/O. Once the MOVX class instruction is executed, the microcontroller will generate a falling edge on the RD or WR (according to the input or output instruction) pin. The waveform of this falling edge is ORed with P2.7 and will also be generated at the output of the OR gate. A falling edge, this falling edge will cause the output of the 74HC244 to be connected to the input, so that the data of the input device can be read from the bus by the MCS-51 microcontroller.
It should be noted that the 74HC244 is not latched. Therefore, if the data provided by the input device is relatively short, it is extended by a chip with a latch. Such as 74HC373, 74HC573 and so on.
2 Extension of Output Interface
Since the data bus of the microcontroller is for each chip, it is generally impossible to maintain a state for one output, therefore, The main function of the output interface is to perform data retention (ie, data latching), that is, the expansion of the output interface is actually an extended latch.
2.1 74HC377 chip function
Output interface expansion is usually implemented with 74HC377 chip. The chip is an 8D latch with an enable terminal. The pins of the chip are shown in Figure 4. The functions of the relevant pins are as follows:
◇D0~D7 are 8-bit data inputs. ;
◇Q0~Q7 are 8-bit data output terminals;
◇G is the enable control terminal;
◇CLK is the clock signal, and the rising edge latches the data.
Table 1 lists the truth table for the chip.
2.2 Application 74HC377 chip expansion output interface
Figure 5 is a circuit connection diagram for the output interface expansion using the 74HC377. In the figure, the G terminal of the 74HC377 is connected to the P2.6 port, and its address is x0xxxxxxB. If "all" is set to 1, it is 1011 1111 1111 1111B, so that 0BFFFH is the address of the chip.
Since the WR of the MCS-51 is connected to the CLK terminal of the 74HC377, when the WR signal goes from low to high, the data on the data bus is the output data. When P2.6 outputs low level, G is valid, so the data is latched. The related procedures are as follows:
MOV DPTR, #0BFFFH
MOV A,#DATA
MOVX @DPTR,A
In addition, using the 74HC373 chip, The 74HC573 chip can also be used to expand the P0 port.
3 Interface Extension Instances
In an actual application system, it may be necessary to expand multiple I/O ports at the same time to meet the needs of the application system. Each input and output expansion I/O chip should be "single address" by the 74LS138 to decode the data bus DB (DataBus). In order to prevent the influence of transition interference on the decoding strobe logic, the peripheral chips used in the MCU system are generally set to the two-step strobe mode, that is, in addition to the configuration of the decode strobe, the enable strobe should be configured. The 74HC244 chip itself has no obvious chip select and read/write control terminals. The design usually uses decoding and read control signals to simultaneously control the CS of the 74HC244, thus effectively suppressing the transient interference of the input/output data information.
This circuit input port is extended by two 74HC244. The input terminal is connected to a keyboard or other digital signal; and the output port expansion uses two 74HC377 for controlling the digital tube, LED, relay, and the like. The detailed circuit schematic is shown in Figure 6.
The part of the code is as follows:
The data/address/control bus port of 51 MCU has a certain load capacity, and the P0 port can drive 8 TTL gate circuits. P1 port, P2 port and P3 port can drive 4 TTL gate circuits. If the load exceeds the above regulations, the driver should be added. The bus driver can use TTL type three-state buffer gate circuits 74HC244, 74HC245. In addition, while extending the port line, you should also consider the configuration of the bus driver, pay attention to the bus load balancing configuration. Properly installing pull-up resistors on the bus improves the reliability of bus signal transmission.
In addition, a system may malfunction due to various interferences and unstable factors. To solve this problem, some measures can be taken from the software design.
4 Conclusion
Compared with other 51 single-chip microcomputer P0 port expansion, the P0 parallel expansion method of the input/output port introduced in this paper can easily realize P0 port. Parallel extension. The designed interface expansion circuit has been successfully used in practical systems. The actual operation shows that the P0 port system extended by this method can operate reliably and stably.