STM32 clock system detailed

1. In STM32, there are five clock sources, HSI, HSE, LSI, LSE, PLL.

1, HSI is a high-speed internal clock, RC oscillator, frequency is 8MHz.

2, HSE is a high-speed external clock, can be connected to a quartz /ceramic resonator, or connected to an external clock source, the frequency range is 4MHz ~ 16MHz.

3, LSI is a low-speed internal clock, RC oscillator, frequency is 40kHz.

4. The LSE is a low-speed external clock connected to a quartz crystal with a frequency of 32.768 kHz.

5, PLL is the phase-locked loop multi-frequency output, its clock input source can be selected as HSI/2, HSE or HSE/2. The multiplier can be selected from 2 to 16 times, but its output frequency must not exceed 72 MHz.

2.STM32 has three different clock sources that can be used to drive the system clock (SYSCLK):

1: HSI oscillator clock (internal clock)

2: HSE oscillator clock (external clock, provided by crystal oscillator)

3: PLL clock (phase-locked loop clock)

3. The RTC clock can be derived from three clock sources:

1: LSE oscillator clock

2: LSI oscillator clock

3:HSE/128

4. Independent watchdog IWDG uses LSI

5.STM32 has a full-speed USB module whose serial interface engine requires a clock source with a frequency of 48MHz. This clock source can only be taken from the PLL output. It can be selected to be divided by 1.5 or 1 by one. That is, when a USB module is required, the PLL must be enabled and the clock frequency configured to 48MHz or 72MHz.

6.STM32 can also select a clock signal output to the MCO pin (PA8)

1, PLL/2

2, HSI oscillator clock

3, HSE oscillator clock

4, system clock SYSCLK

System clock SYSCLK, which is the clock source for most of the components in STM32. The system clock can be selected as PLL output, HSI or HSE. The maximum clock frequency of the system clock is 72MHz. It is divided by the AHB divider and sent to each module. The AHB divider can be divided by 1, 2, 4, 8, 16, 64, 128, 256, and 512. The clock output from the AHB divider is sent to the 5 modules:

1. The HCLK clock is sent to the AHB bus, core, memory and DMA.

2. The system timer clock is sent to Cortex after being divided by 8.

3, directly to the Cortex idle running clock FCLK.

4, to the APB1 divider. The APB1 divider can be divided by 1, 2, 4, 8, and 16. The output is used by the APB1 peripheral (PCLK1, maximum frequency 36MHz), and the other is sent to the timer (Timer) 2, 3, 4 times. Used by the device. The multiplier can be selected for 1 or 2 octaves, and the clock output is used by timers 2, 3, and 4.

5. Give the APB2 divider. The APB2 divider can be divided by 1, 2, 4, 8, and 16. The output is used by the APB2 peripheral (PCLK2, maximum frequency 72MHz), and the other is sent to the Timer 1 multiplier. The multiplier can be selected for 1 or 2 multiplied, and the clock output is used by Timer 1. In addition, the APB2 divider has an output for the ADC divider, which is divided and sent to the ADC module for use. The ADC divider can be divided by 2, 4, 6, and 8.

Among the above clock outputs, many are enabled with control, such as AHB bus clock, core clock, various APB1 peripherals, APB2 peripherals, and so on. When you need to use a module, remember to enable the corresponding clock first.

Note that the multiplier of the timer, when the crossover of the APB is 1, its multiplier value is 1, otherwise its multiplier value is 2.

Devices connected to APB1 (low-speed peripherals) include: power interface, backup interface, CAN, USB, I2C1, I2C2, UART2, UART3, SPI2, window watchdog, Timer2, Timer3, and Timer4. Note that the USB module requires a separate 48MHz clock signal, but it should not be the clock for the USB module to operate, but only the clock used by the Serial Interface Engine (SIE). The clock for the USB module to operate should be provided by APB1.

The devices connected to APB2 (high-speed peripherals) are: UART1, SPI1, Timer1, ADC1, ADC2, all common IO ports (PA~PE), and second function IO ports.