FPGA clock edge sampling problem

As we all know, the clock is like the heart to the human body relative to the FPGA. In the sequential logic design, the processing of each signal is closely related to the clock. We usually take the edge trigger of the clock as the trigger condition of the signal. So how does the system process the signal on the clock edge?

False the following procedure: moduel test (clk, a, b);

input clk;

input a;

output b;

always @ (posedge clk)

begin b<=a; end

endmodule

The above procedure, if A changes on the rising edge of the clock, then B Will be assigned when the next clock edge arrives. In this way, in our general thinking, this idea will be formed: after the clock acquires the data, the next clock edge will be assigned. However, write the testbench file so that a is assigned a value of 1 at 15ps and a clock period of 10ps. The waveform is that A and B are assigned a value of 1 on the rising edge of the clock. Why is this?

In fact, our traditional thinking is wrong. The reason why B will change when the next clock edge comes is because the system did not collect the change of A on the previous rising edge. In the second The value of A is collected when the rising edge comes, and is directly assigned to B. In testbench, A has been assigned a value of 1 at 15ps, so the clock edge is assigned to the change of A and is directly assigned to B. In fact, if it is not ideal, the assignment of B will be held for a period of time after the clock edge changes, because the assignment will have a small time delay.

Since the assignment is mentioned, let's talk about the difference between blocking assignment and non-blocking assignment. In fact, if it is in a different process, there is no difference between blocking assignment and non-blocking assignment. It is only when there is a variable value assigned to another variable in the same process. At this time, the non-blocking assignment is equivalent to parallel execution, and the blocking assignment is equivalent to sequential execution.