Linux kernel interrupt mechanism analysis

Summary: This paper mainly analyzes the Linux 2.4.0 kernel device interrupt process from the perspective of kernel implementation. This article is written for readers and Linux driver developers who want to learn about the Linux I/O subsystem.

Keywords: Linux, Interrupts, Device Drivers

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Welcome to the errors and concerns in the documentation.

§5.1 I386 Interrupts and Exceptions

Interrupts are usually divided into two categories: "synchronous interrupt" and asynchronous interrupt. Synchronous interrupt refers to the interrupt generated by the CPU control unit when the instruction is executed. It is called “synchronous interrupt” because the CPU will only issue such an interrupt signal after an instruction is aborted. Asynchronous interrupt refers to the interrupt signal randomly generated by other hardware devices according to the CPU clock.

In the Intel 80x86 CPU manual, synchronous and asynchronous interrupts are also referred to as "Exception" and "Interrupt", respectively. Intel has broken down interrupts and exceptions into the following categories in detail:

(1) Interrupts

1. Maskable Interrupt: This type of interrupt is sent to the INTR of the CPU. The pin can be turned off by clearing the IF flag of the eflag register.

2. Nonmaskable Interrupt: It is sent to the NMI pin of the CPU. Usually only a few critical events, such as hardware failure, generate a non-maskable interrupt signal. The IF flag in register eflag has no effect on this type of interrupt.

(2) Exception

1. Processor-detected exception: An exception generated by an abnormal condition detected when the CPU executes an instruction. According to the value stored in the kernel state stack eip register when the CPU control unit generates an exception, such an exception can be subdivided into three types:

n Fault (Fault): The value stored in the eip is faulty. The instruction address, so the instruction will be re-executed after the exception handler ends. & ldquo; page faults & rdquo; is a common example of such anomalies.

n Trap: The value stored in eip is an instruction address, but the instruction is after the instruction address that caused the trap. The trap is only triggered when it is not necessary to re-execute the executed instructions. Its main purpose is to debug the program.

n Abort: When a serious error occurs, the CPU control unit cannot save meaningful values ​​in the eip register except for trouble. Abnormal aborts are usually caused by hardware failures or invalid values ​​in the system tables. This interrupt generated by the CPU control unit is an emergency signal used to switch the execution path of the CPU to an aborted handler, and the corresponding ISR typically has no choice but to force the affected process to abort.

2. Programming Exception: Also commonly referred to as "software interrupt", is an interrupt that occurs when a programmer issues an interrupt request, such as an int instruction and an int3 instruction. . A programming exception is also caused when the conditions of the into (check overflow) and bound (check address out of bounds) instructions are not true. The CPU control unit treats the programming exception as a Trap. This type of exception has two typical uses: one is to execute the system call; the other is to notify the debugger of a specific condition.

5.1.1 Interrupt Vectors

Each interrupt and exception can be identified by an unsigned integer between 0 and 255. Intel calls it “ Interrupt Vector (Interrupt) Vector)”. In general, the interrupt vector for non-maskable interrupts and exceptions is fixed, and the interrupt vector for maskable interrupts can be programmed to change the interrupt controller. The 256 interrupt vectors of the I386 CPU are allocated as follows:

1. A total of 32 vectors from 0-31 are used for exception and non-maskable interrupts.

2. A total of 16 vectors from 32-47 are used for maskable interrupts, corresponding to the IRQ input lines of the master and slave 8259A interrupt controllers.

3. The remaining 48-255 are used to identify soft interrupts.

Linux uses vectors between 0 and 47. But for the soft interrupt vector between 48-255, Linux uses only one of them, the interrupt vector 128 (0x80) used to implement the system call. When a user-mode process executes an int 0x80 assembly instruction, the CPU switches to kernel mode to service the system call.

Linux defines the macro FIRST_EXTERNAL_VECTOR in the header file include/asm-i386/hw_irq.h to indicate the interrupt vector corresponding to the first peripheral interrupt (ie IRQ0 of 8259A). In addition, SYSCALL_VECTOR is defined. Represents the interrupt vector used for system calls. As shown below:

/*

* IDT vectors usable for external interrupt sources start

* at 0x20:

*/

#define FIRST_EXTERNAL_VECTOR 0x20

#define SYSCALL_VECTOR 0x80

5.1.2 I386 IDT

The i386 CPU IDT table has a total of 256 entries, one for each interrupt. vector. Each entry is an interrupt descriptor that describes the corresponding interrupt vector. The interrupt vector is the index of the descriptor in the IDT. Each interrupt descriptor is 8 bytes in size. According to INTEL's terminology, the interrupt descriptor is also called "Gate".

The interrupt descriptor has the following four types:

(1) Task Gate: Contains the TSS segment selector of a process. Whenever an interrupt signal occurs, it is used to replace the TSS segment selector of the current process. Linux does not use tasks. The format of the tasks is as follows:

(2) Interrupt Gate: The interrupt gate contains a segment selector and an intra-segment offset of an interrupt handler. Note that when the I386 CPU traverses an interrupt gate into the corresponding interrupt handler, it clears the IF flag in the eflag register, thereby masking the next possible maskable interrupt.

(3) Trap Gate: Similar to the interrupt gate, except that the CPU does not clear the IF flag when it is transferred to the interrupt handler through the trap gate.

(4) Call Gate: Linux does not use the call gate.

The format of these three types of doors is shown in Figure 5-2.

5.1.3 Interrupt Controller 8259A

We all know that two cascaded 8359A PIC (Programmable Interrupt Controller, PIC for short) are used in the PC. ) to manage interrupt signals from system peripherals. Each 8259A PIC provides eight IRQ (Interrupt ReQuest, Interrupt Request, IRQ) input lines. In cascade mode, the Master 8259A PIC (first PIC) interrupt signal input line IR2 is used to cascade the INT pin of the Slave 8259A PIC (second PIC), so the two 8259A can provide a total of 15 available. IRQ input line. As shown below:

Figure 5-3 Cascading of the master and slave 8259A interrupt controllers

5.1.3.1 Basic Principles of the 8259A PIC